1. Field of the Invention
The present invention relates to a data processing device and a control method of the data processing device. Particularly, the present invention relates to a data processing device including a program execution section that supplies an operation direction signal to a peripheral device based on an executed program and executes a branch operation in response to a branch direction signal, and a control method of the data processing device.
2. Description of Related Art
In a recent data processing device such as a microcomputer, program parallel processing is executed in order to improve processing performance. For example, the data processing device includes a program execution section that executes an instruction based on a program and a peripheral device (e.g. coprocessor) that operates based on operation direction from the program execution section. When an instruction to use the coprocessor in the program being executed in the program execution section occurs, the program execution section gives an operation direction to the coprocessor and executes the instruction subsequent to the operation direction. In such a configuration, the program execution section and the coprocessor can execute processing in parallel with each other. An example of the data processing device that performs such parallel processing is disclosed in Japanese Unexamined Patent Application Publication No. 1-109466 (Iwasaki et al.).
FIG. 8 is a block diagram of a data processing device 100 disclosed in Iwasaki et al. Referring to FIG. 8, the data processing device 100 includes a central processing unit (CPU) 101, a coprocessor 102, a main storage 103, an address bus 104 and a data bus 105. In the data processing device 100, the CPU 101, the coprocessor 102 and the main storage 103 are connected through the address bus 104 and the data bus 105. The address bus 104 is a bus to transfer an address indicating destination of data transmission and reception. The data bus 105 is a bus to transfer data to be transmitted and received. In the data processing device 100, the CPU 101 executes a program stored in the main storage 103. Further, the CPU 101 outputs an operation direction to the coprocessor 102 according to the program. The coprocessor 102 includes a status port 121, a command port 122, an operand port 123 and an execution unit 124. The status port 121 is a port that, when an exception occurs as a result of execution processing in the coprocessor 102, outputs the description of the exception to the CPU 101. The command port 122 is a port for the CPU 101 to write the description of the instruction to the coprocessor 102. The operand port 123 is a port that is used when it is necessary for the CPU 101 to supply operand data needed to the processing of the coprocessor 102 or when it is necessary to write data back from the coprocessor 102 to the CPU 101. The execution unit 124 executes the processing based on data supplied via the command port 122 and the operand port 123. Then, the execution unit 124 outputs CPEND signal, CPERR signal and BUSY signal to the CPU 101 according to the execution state of the processing.
FIG. 9 is a timing chart showing the operation of the data processing device 100. Referring to FIG. 9, when an instruction to be transferred to the coprocessor 102 occurs, the CPU 101 designates the command port 122 using the address bus 104 and transmits an operand code to the command port 122 through the data bus 105. Then, the coprocessor 102 activates the BUSY signal, receives the operand code transmitted from the CPU 101 and starts processing. Further, the coprocessor 102 notifies that it has received the operand code correctly to the CPU 101 by inactivating the CPERR signal. On the other hand, the CPU 101 continues to execute the next program processing after the issue of the instruction to the coprocessor 102 is completed. In this manner, in the data processing device 100, the CPU 101 continues the program processing after transferring the instruction to the coprocessor 102, thereby realizing parallel processing in the CPU 101 and the coprocessor 102.
The operation of the data processing device 100 in the event that an exception occurs in the processing being executed in the coprocessor 102 of the data processing device 100 is described hereinafter. As shown in FIG. 9, when an exception occurs in the processing being executed in the coprocessor 102, the coprocessor 102 becomes suspended with the exception pending in the status port 121. Even in such a case, when an instruction to be transferred to the coprocessor 102 occurs, the CPU 101 designates the command port 122 using the address bus 104 and transmits an operand code to the command port 122 through the data bus 105. Then, the coprocessor 102 activates the BUSY signal and receives the operand code transmitted from the CPU 101. However, because the exception has occurred in the previous processing, the coprocessor 102 keeps the CPERR signal active. Further, the CPU 101 reads that the CPEND signal output from the coprocessor 102 is inactive when transferring the operand code and thereby recognizes that the processing of the coprocessor 102 is not yet completed. Then, at the rising edge of the BUSY signal, the CPU 101 designates the status port 121 using the address bus 104 and reads the status information through the data bus 105. The CPU 101 thereby recognizes that the exception is occurring in the processing performed previously in the coprocessor 102 and executes exception handling on the previous processing.